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publication number s72ns-p_00 revision 01 issue date september 6, 2006 s72ns-p based mcps/pops s72ns-p based mcps/pops cover sheet mirrorbit ? flash memory and dram 128/256/512 mb (8/16/32 m x 16 bit), 1.8 volt-only, multiplexed simultaneous read/write, burst mode flash memory 128/256 mb (8/16 m x 16 bit) ddr dram on split bus data sheet (advance information) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
ii s72ns-p based mcps/pops september 6, 2006 s72ns-p_00-01 data sheet (advance information) notice on data sheet designations spansion inc. issues data sheets with advance informat ion or preliminary designati ons to advise readers of product information or intended s pecifications throughout the produc t life cycle, including development, qualification, initial production, and full production. in all cases, however, reader s are encouraged to verify that they have the latest information before finalizi ng their design. the following descriptions of spansion data sheet designations are presented here to hi ghlight their presenc e and definitions. advance information the advance information designation i ndicates that spansion inc. is de veloping one or more specific products, but has not committed any des ign to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore plac es the following conditions upo n advance information content: ?this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has pr ogressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under c onsideration. spansion places the following conditi ons upon preliminary content: ?this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designati ons (advance information, preliminary, or full production). th is type of document distinguishes t hese products and their designations wherever necessary, typically on the first page, th e ordering information page, and pages with the dc characteristics table and the ac er ase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of ti me such that no changes or only nominal changes are expected, the preliminary desi gnation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the a ddition or deletion of a speed option, temperat ure range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographic al error or incorrect specificati on. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these doc ument designations may be directed to your local spansion sales office.
this document contains information on one or more products under development at spansion inc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed pr oduct without notice. publication number s72ns-p_00 revision 01 issue date september 6, 2006 features ? power supply voltage of 1.7 v to 1.95 v ? burst speeds ? flash = 66 mhz, 80 mhz ? dram = 133 mhz ? packages ? 11.0 x 10.0 mm, 133-ball mcp ? 8.0 x 8.0 mm, 133-ball mcp ? 12.0 x 12.0 mm, 128-ball pop ? operating temperature of ?25c to +85c general description this document contains information on th e s72ns-p mcp stacked products. refer to the s29ns-p data sheet (s29ns-p_00) for full electrical specifications of the flash memory component. the s72ns series is a product line of stack ed products (mcps and pops), and consists of: ? ns family multiplexed flash memory die ? ddr dram the products covered by this documen t are listed in th e tables below. for detailed specifications, please refer to the individual data sheets. s72ns-p based mcps/pops mirrorbit ? flash memory and dram 128/256/512 mb (8/16/32 m x 16 bit), 1.8 volt-only, multiplexed simultaneous read/write, burst mode flash memory 128/256 mb (8/16 m x 16 bit) ddr dram on split bus data sheet (advance information) flash density dram density 128 mb 256 mb 128 mb s72ns128pd0 256 mb S72NS256Pd0 512 mb s72ns512pd0 s72ns512pe0 density manufacturer publication number 128 dram1 sdram_03 dram5 sdram_07 density manufacturer publication number 256 dram1 tbd dram5 sdram_11
2 s72ns-p based mcps/pops s72ns-p_00_01 september 6, 2006 data sheet (advance information) 1. product selector guide device opn flash density ddr dram density flash speed (mhz) ddr dram speed (mhz) supplier package s72ns128pd0ajbgg 128 mb 128 mb 66 133 dram1 8.0 x 8.0mm133-ball mcp s72ns128pd0ajbgc 80 s72ns128pd0ajblg 66 dram5 s72ns128pd0ajblc 80 s72ns128pd0kjfgg 128 mb 128 mb 66 133 dram1 12.0 x 12.0mm 128-ball pop s72ns128pd0kjfgc 80 s72ns128pd0kjflg 66 dram5 s72ns128pd0kjflc 80 S72NS256Pd0ajbgg 256 mb 128 mb 66 133 dram1 8.0 x 8.0mm133-ball mcp S72NS256Pd0ajbgc 80 S72NS256Pd0ajblg 66 dram5 S72NS256Pd0ajblc 80 S72NS256Pd0kjfgg 256 mb 128 mb 66 133 dram1 12.0 x 12.0mm 128-ball pop S72NS256Pd0kjfgc 80 S72NS256Pd0kjflg 66 dram5 S72NS256Pd0kjflc 80 s72ns512pd0ajggg 512 mb 128 mb 66 133 dram1 11.0 x 10.0mm 133-ball mcp s72ns512pd0ajggc 80 s72ns512pd0ajglg 66 dram5 s72ns512pd0ajglc 80 s72ns512pd0kjfgg 512 mb 128 mb 66 133 dram1 12.0 x 12.0mm 128-ball pop s72ns512pd0kjfgc 80 s72ns512pd0kjflg 66 dram5 s72ns512pd0kjflc 80 s72ns512pe0ajggg 512 mb 256 mb 66 133 dram1 11.0 x 10.0mm 133-ball mcp s72ns512pe0ajggc 80 s72ns512pe0ajglg 66 dram5 s72ns512pe0ajglc 80 s72ns512pe0kjfgg 512 mb 256 mb 66 133 dram1 12.0 x 12.0mm 128-ball pop s72ns512pe0kjfgc 80 s72ns512pe0kjflg 66 dram5 s72ns512pe0kjflc 80
s72ns-p_00_01 september 6, 2006 s72ns-p based mcps/pops 3 data sheet (advance information) 2. product block diagram notes: 1. amax indicates highest address bit for memory component: a. amax = a24 for ns512p, a 23 for ns256p, a22 for ns128p b. amax = a11 for 128 mb ddr dram c. amax = a12 for 256mb ddr dram 2. for flash, a15 - a0 is tied to dq15 - dq0. mux flash memory ns-p ddr dram memory f-rst# f-acc f-wp# f-ce# f-oe# f-we# avd# f-v ss rst# acc wp# ce# oe# we# avd# v ss adq15-adq0 f-clk f-rdy amax - a16 f-v cc f-v ccq a15-a0 dq15-dq0 clk rdy v cc v ccq d-ras# d-cas# d-ba0 d-ba1 d-cke d-we# d-amax - d-a0 d-v cc ras# cas# ba0 ba1 cke we# v cc d-v ccq v ccq clk clk# dqs0 dqs1 ldqm udqm test dq15-dq0 v ss v ssq d-clk d-clk# d-ldqs d-udqs d-ldqm d-udqm d-test d-dq15 - d-dq0 d-v ss d-v ssq f2-ce# amax - a16 d-ce# ce#
4 s72ns-p based mcps/pops s72ns-p_00_01 september 6, 2006 data sheet (advance information) 3. connection diagrams figure 3.1 133-ball fine-pitch ball grid array mcp note: additional nc locations are in reference to the superset connection diagram shown here device opn flash address amax ddr dram address amax additional nc locations s72ns128pd0 a22 a11 ball f1, ball e1, ball n11 S72NS256Pd0 a23 a11 ball e1, ball n11 s72ns512pd0 a24 a11 ball n11 s72ns512pe0 a24 a12 n/a 3 2910 5 47 68 1 13 12 14 11 d-vssq dnu d-vcc d-dq5 d-dq9 d-vccq d-vss d-dq8 d-vcc dnu dnu d-vssq dnu d-dq3 b d e f g h j k l m n p a c d-dq13 d-vss d-ldqm d-dq6 d-dq10 d-udqs d-vccq d-vssq d-vccq dnu d-vccq d-dq1 dnu d-dq4 d-dq14 d-dq15 d-vssq d-dq7 d-dq11 d-dq12 d-vss d-udqm d-vcc d-vcc d-dq0 d-dq2 d-vss d-ldqs nc nc index rfu adq8 f-oe# d-vcc a17 a22 a24 adq1 adq9 adq0 a18 a19 a23 adq3 f-vss adq2 f-we# f-wp# f-ce# adq11 f-vccq adq10 f-clk f-vcc f-acc adq12 adq13 adq4 nc f-vss a16 f-vss f-vss adq5 nc f-avd# a21 adq7 nc adq6 d-ce# f-rst# a20 adq15 f-vccq adq14 d-a3 nc d-a10 d-a1 d-a9 d-a6 d-vss d-cke d-we# nc f-rdy nc f-vss nc d-vcc d-vss d-a11 d-a2 d-a8 d-a5 d-clk# d-cas# d-ba1 dnu f-vcc nc dnu d-a12 nc dnu d-ba0 d-a0 d-a7 d-a4 d-clk d-ras# d-vcc dnu dnu d-vss dnu d-vcc legend index location do not use no connect dram only code flash only reserved for future use
s72ns-p_00_01 september 6, 2006 s72ns-p based mcps/pops 5 data sheet (advance information) figure 3.2 128-ball fine-pitch ball grid array, pop note: additional nc locations are in reference to the superset connection diagram shown here. device opn flash address amax ddr dram address amax additional nc locations s72ns128pd0 a22 a11 ball k1, ball t2, ball u10 S72NS256Pd0 a23 a11 ball k1, ball u10 s72ns512pd0 a24 a11 ball u10 s72ns512pe0 a24 a12 n/a 3 2910 5 47 68 1 13 12 15 14 17 16 18 11 adq8 nc adq14 adq15 adq10 adq9 adq12 adq11 adq13 nc d-vccq d-vss d-vcc d-vccq d-vssq d-vcc nc d-vss b d e f g h j k l m n p r t u v a c adq0 nc adq6 adq7 adq2 adq1 adq4 adq3 adq5 nc d-vccq d-vss d-vccq d-vccq nc d-vcc d-vssq f-clk f-oe# f-avd# d-vssq d-vssq f-rdy f-rst# d-udqs d-dq15 f-we# f-vccq d-dq13 d-dq14 f-vss f-vccq d-dq11 d-dq12 f-vss f-vss d-dq9 d-dq10 f-vss f-vss d-dq8 d-udqm f-vss f-vss d-clk d-clk# f1-ce# a23 ldqm d-dq07 a18 a20 d-dq6 d-dq5 a16 a21 d-dq4 d-dq3 a19 f-acc d-dq2 d-dq1 f-vcc f-vcc d-dq0 d-ldqs a22 a17 d-vccq d-vssq a24 nc d-vcc d-vssq nc nc d-cke d-a12 d-ce# nc d-a1 d-a3 d-a10 f-wp# d-a9 d-we# d-cas# d-a7 nc d-a5 d-vss d-a11 nc nc d-ba1 d-ba0 d-vcc nc d-a2 d-vcc d-a0 nc nc d-vss d-ras# d-a8 d-a4 d-a6 nc d-vss legend no connect nor flash only ddr dram only
6 s72ns-p based mcps/pops s72ns-p_00_01 september 6, 2006 data sheet (advance information) 4. input/output descriptions signal description flash dram amax ? a16 = flash address inputs adq15 ? adq0 = flash multiplexed address and data f-ce# = flash chip-enable input. asynchronous relative to clk for burst mode x f-oe# = flash output enable input. asynchronous relative to clk for burst mode. x f-we# = flash write enable input x f-vcc = flash device power supply (1.7 v to 1.95 v) x f-vccq = flash input/output buffer power supply x f-vss = flash ground x f-rdy = flash ready output. indicates the status of the burst read. v ol = data invalid. v oh = data valid. x f-clk = flash clock. the first rising edge of clk in conjunction with avd# low latches the address input and activates burst mode operation. after the initial word is output, subsequent rising edges of clk increment the internal address counter. clk should remain low during asynchronous access. x f-avd# = flash address valid input. indicates to device that the valid address is present on the address inputs. v il = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of clk. v ih = device ignores address inputs x f-rst# = flash hardware reset input. v il = device resets and returns to reading array data x f-wp# = flash hardware write protect input. v il = disables program and erase functions in the four outermost sectors x f-acc = flash accelerated input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. x d-a12 ? d-a0 = dram address inputs. x d-dq15 ? d-dq0 = dram data input/output x d-clk = dram system clock x d-ce# = dram chip select x d-cke = dram clock enable x d-ba1 ? ba0 = dram bank select x d-ras# = dram row address strobe x d-cas# = dram column address strobe x d-udqm ? d-ldqm = dram data input mask x d-we# = dram write enable input x d-vss = dram ground x d-vssq = dram input/output buffer ground x d-vccq = dram input/output buffer power supply x d-vcc = dram device power supply x d-udqs = dram upper data strobe, output with read data and input with write data x d-ldqs = dram lower data strobe, output with read data and input with write data x d-clk# = ddr clock for negative edge of clk x rfu = reserved for future use nc = no connect. can be connected to ground or left floating. dnu = do not use. this signal must be left floating
s72ns-p_00_01 september 6, 2006 s72ns-p based mcps/pops 7 data sheet (advance information) 5. ordering information the order number (valid combinatio n) is formed by the following: notes: 1. packing type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. 3. valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s72ns 256 p d0 aj b l g 3 pack in g t y pe 0 = tray 2 = 7-inch tape and reel 3 = 13-inch tape and reel flash and ddr speed g = 66 mhz flash, 133 mhz ddr dram c = 80 mhz flash, 133 mhz ddr dram ddr supplier g = dram type 1 x16 ddr dram l = dram type 5 x16 ddr dram package modifier g = 133-ball, 11x10mm, fbga mcp b = 133-ball, 8x8mm, fbga mcp f = 128-ball, 12x12mm, fbga pop package and material type aj = thin profile fine-pitch bga pb-free lf35 mcp (0.5 mm pitch) kj = thin profile fine-pitch bga pb-free pop (0.65 mm pitch) ddr dram and data flash density d0 = 128 mb dram, no data flash e0 = 256 mb dram, no data flash process technology p = 90 nm, mirrorbit tm technology code flash density 512 = 512 mb 256 = 256 mb 128 = 128 mb product family s72ns multi-chip product (mcp) 1.8 v multiplexed, srw, burst mode flash and ddr dram on split bus valid combinations product family code flash density (mb) process technology dram density (mb) package type/ material ddr vendor flash & ddr speed packing type s72ns 128 p d0 ajb, kjf g, l g, c 0, 2, 3 (note 1) 256 g, c 512 ajg, kjf d0, e0
8 s72ns-p based mcps/pops s72ns-p_00_01 september 6, 2006 data sheet (advance information) 6. physical dimensions 6.1 nlc133?133-ball fine-pitch ball grid array (fbga) 11.0 x 10.0 mm 3436 \ 16-039.22 \ 12.09.04 package nlc 133 jedec n/a d x e 11.0 mm x 10.00 mm package symbol min nom max note a 0.90 1.00 1.10 profile a1 0.20 0.25 0.30 ball height a2 0.70 0.76 0.82 body thickness d 10.9 11.0 11.1 body size e 9.9 10.0 10.1 body size d1 6.50 bsc. matrix footprint e1 6.50 bsc. matrix footprint md 14 matrix size d direction me 14 matrix size e direction n 133 ball count ?b 0.25 0.30 0.35 ball diameter ee 0.50 bsc. ball pitch ed 0.50 bsc ball pitch sd / se 0.25 bsc. solder ball placement d5-d11, e4-e11, f4-f11 depopulated solder balls g4-g11, h4-h11, j4-j11 k4-k11, l4-l11 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means.
s72ns-p_00_01 september 6, 2006 s72ns-p based mcps/pops 9 data sheet (advance information) 6.2 nsc133?133-ball fine-pitch ba ll grid array (fbga) 8.0 x 8.0 mm package nsc 133 jedec n/a d x e 8.00 mm x 8.00 mm note package symbol min nom max a 0.90 1.00 1.10 profile a1 0.20 0.25 0.30 ball height a2 0.70 0.76 0.82 body thickness d 8.00 bsc body size e 8.00 bsc body size d1 6.50 bsc. matrix footprint e1 6.50 bsc. matrix footprint md 14 matrix size d direction me 14 matrix size e direction n 133 ball count ?b 0.25 0.30 0.35 ball diameter ee 0.50 bsc. ball pitch ed 0.50 bsc ball pitch sd / se 0.25 bsc. solder ball placement d5-d11,e4-e11,f4-f11,g4-g11 depopulated solder balls h4-h11,j4-j11,k4-k11,l4-l11 3583 \ 16-039.22 \ 8.15.06 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1 spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means.
10 s72ns-p based mcps/pops s72ns-p_00_01 september 6, 2006 data sheet (advance information) 6.3 alj128?128-ball fine-p itch ball grid array (fbga) 12.0 x 12.0 mm 3561 16 038 2 4\5156 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 3.0, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. n is the maximum number of balls on the fbga package. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 outline and dimensions per customer requirement. package alj 128 jedec n/a d x e 12.00 mm x 12.00 mm package symbol min nom max note a --- --- 1.15 profile a1 0.35 --- --- ball height a2 0.60 --- 0.72 body thickness d 12.00 bsc. body size e 12.00 bsc. body size d1 11.05 bsc. matrix footprint e1 11.05 bsc. matrix footprint md 18 matrix size d direction me 18 matrix size e direction n 128 ball count n 128 maximum number of balls r 2 number of land perimeters ?b 0.40 0.45 0.50 ball diameter ee 0.65 bsc. ball pitch ed 0.65 bsc ball pitch se / sd 0.325 bsc. solder ball placement depopulated solder balls r3~r16, t3~t16 c3~c16, d3~d16, e3~e16, f3~f16 g3~g16, h3~h16, j3~j16, k3~k16 l3~l16, m3~m16, n3~n16, p3~p16 c 6 b side view 0.10 c 128x a1 0.15 m c a b 0.08 m c 7 se e1 d1 7 18 17 13 12 14 15 16 10 7 8 9 11 6 5 2 3 4 ee sd ed a pin a1 corner d b c h f g e m l k j t r p n bottom view 1 v u c a d e index mark 9 corner pin a1 c b 0.10 0.10 (2x) top view c 0.10 (2x) a2 a
s72ns-p_00_01 september 6, 2006 s72ns-p based mcps/pops 11 data sheet (advance information) 6.4 asf128?128-ball fine-pitch ball grid array (fbga) 12.0 x 12.0 mm 3581\16-039.24\8.3.6 package asf128 jedec n/a d x e 12.00 mm x 12.00 mm package symbol min nom max note a 0.95 1.05 1.15 profile a1 0.35 0.40 0.45 ball height a2 0.59 --- 0.72 body thickness d 12.00 bsc. body size e 12.00 bsc. body size d1 11.05 bsc. matrix footprint e1 11.05 bsc. matrix footprint md 18 matrix size d direction me 18 matrix size e direction n 128 ball count n 128 maximum number of balls r 2 number of land perimeters ?b 0.40 0.45 0.50 ball diameter ee 0.65 bsc. ball pitch ed 0.65 bsc ball pitch se / sd 0.325 bsc. solder ball placement c3-c16,d3-d16,e3-e16, depopulated solder balls f3-f16,g3-g16,h3-h16, j3-j16,k3-k16,l3-l16, m3-m16,n3-n16,p3-p16, r3-r16,t3-t16 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 3.0, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. n is the maximum number of balls on the fbga package. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 outline and dimensions per customer requirement.
12 s72ns-p based mcps/pops s72ns-p_00_01 september 6, 2006 data sheet (advance information) 7. revision history 7.1 revision 01 (s eptember 6, 2006) initial release. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any ot her warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2006 spansion inc. all rights reserved. spansion, the spansion logo, mirrorbit, ornand, and combinations thereof ar e trademarks of spansion inc. other names are for informational purposes only and may be trademarks of their respective owners.

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